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A Kernel-Based Partitioning Algorithm for Low-Power, Low-Area Overhead Circuit Design Using Don’t-Care Sets
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- 발행일
- 200212
- 출처
- ETRI Journal, v.24 no.6, pp.473-476
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 02MT2200, 초고속 광가입자망 기술, 양재우
- 초록
- This letter proposes an efficient kernelbased partitioning algorithm for reducing area and power dissipation in combinational circuit designs using don’t-care sets. The proposed algorithm decreases power dissipation by partitioning a given circuit using a kernel extracted from the logic. The proposed algorithm also reduces the area overhead by minimizing duplicated gates in the partitioned sub-circuits. The partitioned subcircuits are further optimized utilizing observability don’t-care sets. Experimental results for the MCNC benchmarks show that the proposed algorithm synthesizes circuits that on the average consume 22.5% less power and have 12.7% less area than circuits generated by previous algorithms based on a precomputation scheme.
- KSP 제안 키워드
- Combinational Circuit, Low-Power, Partitioning Algorithm, area overhead, circuit design, low-area, power dissIPation