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Conference Paper Virtual Prototype Based on Aldebarn CPU Core
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Authors
Jae-Jin Lee, Chan Kim, KyungJin Byun, NakWoong Eum
Issue Date
2015-10
Citation
International Conference on Very Large Scale Integration (VLSI-SoC) 2015, pp.303-306
Language
English
Type
Conference Paper
DOI
https://dx.doi.org/10.1109/VLSI-SoC.2015.7314434
Abstract
This paper proposes a virtual prototype based on the Aldebaran CPU core developed independently by ETRI. The virtual prototype provides instruction and function profiling functionality for software optimization as well as standard integration emulation interface (SystemC, Verilog, Netlist, etc.) compatibility, and architecture performance analysis for efficient adoption into a system-level design environment.
KSP Keywords
Performance analysis, Software optimization, System-level Design, Virtual Prototype, design environment