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학술대회 A Hybrid Embedded Compression Codec Engine for Ultra HD Video Application
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박성모, 변경진, 엄낙웅
International Conference on Very Large Scale Integration (VLSI-SoC) 2015, pp.292-296
We proposed an efficient VLSI hardware architecture of the High Efficiency Video Coding (HEVC) using a hybrid embedded compression algorithm for reducing the frame memory bandwidth. This architecture was designed to reduce the memory bandwidth using an adaptive prediction lossy/lossless algorithm. We saved about 50% of the memory access cycles for the reference data compared to a previous algorithm. The PSNR degradation of 0.12 dB on average was proposed algorithm at the compression ratio of 50%. The architecture was implemented in Verilog HDL and synthesized using a Synopsys Design Compiler with a 65nm cell library; the gate count was about 25,000 gates.
KSP 제안 키워드
Adaptive prediction, Cell library, Compression Algorithm, Embedded compression, Frame memory, Memory Access, Memory bandwidth, Reference data, Synopsys Design Compiler, Ultra HD, VLSI hardware architecture