상세정보
학술지
A novel technique for fabricating high reliable trench DMOSFETs using self-align technique and hydrogen annealing
- 발행일
- 200302
- 출처
- IEEE Transactions on Electron Devices, v.50 no.2, pp.378-383
- ISSN
- 0018-9383
- 출판사
- IEEE
- 협약과제
- 01MM3500, 모바일 디스플레이용 SOD 핵심기술 개발, 이진호
- 초록
- A novel technique for fabricating high reliable trench DMOSFETs using three mask layers is realized to obtain cost-effective production capability, higher cell density and current driving capability, and higher reliability. This technique provides a unit cell with 2.3 ~ 2.4 μm pitch and a channel density of 100 Mcell/in2. Specific on-resistance is 0.36 m廓 쨌 cm2with a blocking voltage of 43 V at gate voltage of 10 V and 5 A source-to-drain current. The time to breakdown of gate oxide grown on the hydrogen annealed trench surface is much longer than that of the gate oxide grown on the nonhydrogen annealed trench surface.
- KSP 제안 키워드
- 3 V, Blocking voltage, Cell density, Channel Density, Drain current, Effective production, Gate oxide, Hydrogen annealing, Novel technique, Self-align, Time to Breakdown