In this paper, we have presented the improved IF transceiver architecture and its implementation results on reconfigurable transceiver based on digital IF for multiple wideband CDMA base stations, which have been implemented as ADC, DAC with high speed and resolution and high performance FPGA. The implemented digital IF transceiver has been designed to support multiple frequency allocations and multiple standards by only modifying the programmable software not its hardware as the software defined radio concept. The digital complex quadrature modulation technique has been used for the digital IF transmitter, which is able to combine multiple frequency bands in digital processing block not RF black and to reject the image frequency signals. Also, this method is possible to apply to the baseband digital adaptive predistortion technique. And, the bandpass sampling technique has been used for the digital IF receiver to reduce the sampling rate of ADC. As the implementation results, the FIR and interpolation/decimation half-band filters over 200 taps, digital mixers and digital synthesizers has been implemented on FPGA with 200 million gates for the digital IF transceivers in wideband CDMA base stations. This paper has presented the experiment results on the frequency response and constellation of the implemented digital IF transceiver through back-to-back combining a transmitter with a receiver using a simplified 16QAM physical channel model.
KSP Keywords
Bandpass sampling, Experiment results, Frequency response(FreRes), High Speed, High performance FPGA, IF Receiver, Physical Channel, Sampling rate, Software Defined Radio(SDR), Wideband CDMA, back-to-back
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