상세정보
학술지
Differentially-Tuned Low-Spur PLL Using 65nm CMOS Process
- 발행일
- 201103
- 출처
- Electronics Letters, v.47 no.6, pp.369-371
- ISSN
- 0013-5194
- 출판사
- IET
- 협약과제
- 08MB2800, 45nm급 혼성 SoC용 아날로그 회로기술, 권종기
- 초록
- A differentially-tuned LC-VCO PLL using a transformer-resonator and a loop-phase control scheme is proposed. The phase of a control path between the differential controls is adjusted to suppress spurious tones. The measured results for the proposed PLL, implemented in a CMOS 65nm process, show operation frequencies of 3.5-5.6GHz, phase noise of -118.5dBc/Hz at 1MHz offset, and spur rejection of 73dB, while dissipating 3.2mA at 1V supply. © 2011 The Institution of Engineering and Technology.
- KSP 제안 키워드
- 65nm CMOS, CMOS Process, Control scheme, LC voltage controlled oscillator(LC-VCO), Phase control, Spurious tones, phase noise