BROWSE
Detail
Journal Article
Differentially-tuned low-spur PLL using 65 nm CMOS process
Cited 5 time in 
Share 
Share
- Authors
- S.-J. Yun, H.D. Lee, K.-D. Kim, J.-K. Kwon
- Issue Date
- 2011-03
- Citation
- Electronics Letters, v.47, no.6, pp.369-371
- ISSN
- 0013-5194
- Publisher
- IET
- Language
- English
- Type
- Journal Article
- Abstract
- A differentially-tuned LC-VCO PLL using a transformer-resonator and a loop-phase control scheme is proposed. The phase of a control path between the differential controls is adjusted to suppress spurious tones. The measured results for the proposed PLL, implemented in a CMOS 65nm process, show operation frequencies of 3.5-5.6GHz, phase noise of -118.5dBc/Hz at 1MHz offset, and spur rejection of 73dB, while dissipating 3.2mA at 1V supply. © 2011 The Institution of Engineering and Technology.
- KSP Keywords
- CMOS Process, Control scheme, LC voltage controlled oscillator(LC-VCO), Phase control, Spurious tones, phase noise