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Journal Article Low power digital PLL based TDC using low rate clocks
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Authors
M.J. Park, J.Y. Lee, H.H. Boo, B.H. Mhin, S.D. Kim, M.Y. Park, C.S. Lee, H.K. Yu
Issue Date
2011-07
Citation
Electronics Letters, v.47, no.14, pp.793-794
ISSN
0013-5194
Publisher
IET
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.1049/el.2011.1426
Abstract
A time-to-digital converter (TDC) using a low rate clock is presented. A simple TDC, capable of decreasing power consumption and solving the metastability problem by using low-rate clocks to detect the fine fractional time difference between the reference clock and digitally controlled oscillator (DCO) clock, is presented. The proposed TDC also includes a simple DCO clock period (Tv) calculation algorithm. An all-digital phase-locked loop (ADPLL), fabricated in 90nm CMOS process, dissipates 0.8mA at 1.2V, and achieves 6.25ps period RMS jitter from 2GHz. © 2011 The Institution of Engineering and Technology.
KSP Keywords
All-digital phase-locked loop(ADPLL), CMOS Process, Calculation algorithm, Clock Period, Digital PLL, Digitally controlled oscillator, Low-Power, Low-rate, Power Consumption, Reference clock, Time-to-Digital Converter