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Conference Paper Feasibility Test of Protocol Engines for a New Video System in Packet Communication
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Authors
Hyukje Kwon, Yongseok Choi
Issue Date
2015-02
Citation
International Conference on Computer Research and Development (ICCRD) 2015, pp.85-91
Language
English
Type
Conference Paper
Project Code
14MB1300, Silicon Nanophotonics-based next-generation computer interface platform, Kim Gyungock
Abstract
The layout between the processor and memory in parallel bus is very complex and difficult to place and route. The expansion of memory capacity and bandwidth is limited. A new memory system using an optical connection is proposed. We designed a serial interface using packet communication, and implemented a protocol engine to be executed on the interface. To test the feasibility of the protocol engine, we implemented a video system using an embedded processor on FPGA. The master and slave protocol engines were on the same FPGA, but used the clock differently. We conducted an experiment on the function of the proposed protocol engine between the video frame buffer and memory using a 2x10-Gbps serial link.
KSP Keywords
Embedded processor, Feasibility test, Frame buffer, Memory System, Optical connection, Parallel bus, Serial interface, Video system, memory capacity, place and route, serial link