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Journal Article Asynchronous 2-Phase Protocol Based on Ternary Encoding for On-Chip Interconnect
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Authors
Myeong-Hoon Oh, Seongwoon Kim
Issue Date
2011-10
Citation
ETRI Journal, v.33, no.5, pp.822-825
ISSN
1225-6463
Publisher
한국전자통신연구원 (ETRI)
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.4218/etrij.11.0211.0063
Project Code
10ZB1100, Development support for customer-based convergence components, Eun Soo Nam
Abstract
Level-encoded dual-rail (LEDR) has been widely used in onchip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current-mode multiple valued logics. Using 0.25 μm CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power-delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz. © 2011 Optical Society of America.
KSP Keywords
100 MHz, CMOS Technology, Current-mode(CM), Data transfer, Dual-rail, Encoder and Decoder, Global interconnects, Handshake Protocol, Reduction ratio, Wire length, data rate