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학술지 Prescaler using Complementary Clocking Dynamic Flip-flop
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저자
한선호, 윤용식, 김천수, 유현규, 박문양
발행일
200305
출처
Electronics Letters, v.39 no.9, pp.709-710
ISSN
0013-5194
출판사
IET
DOI
https://dx.doi.org/10.1049/el:20030478
협약과제
02SB1800, 이동통신용 차세대 RF CMOS Transceiver 집적회로 기술 연구, 유현규
초록
A prescaler using complementary clocking dynamic flip-flops (CCD-FF) is presented and implemented in a synthesiser using 0.18 μm CMOS technology. The maximum operating frequency of the proposed CCD-FF is up to about 10 GHz and the prescaler using this flip-flop operates up to 5.1 GHz. The proposed CCD-FF has not only a high operating frequency but also low power consumption since it is based on the scheme of the conventional true single phase clocking (TSPC) flip-flop with no static DC current. The RMS current consumption of designed 16/17 dual-modulus prescaler is only 1.39 mA at 4 GHz.
KSP 제안 키워드
10 Ghz, CMOS Technology, Current consumption, DC current, Dual-modulus prescaler, Flip-flop, RMS current, Single-phase, low power consumption, maximum operating frequency