상세정보
학술지
Hardware-Software Implementation of MPEG-4 Video Codec
- 발행일
- 200312
- 출처
- ETRI Journal, v.25 no.6, pp.489-502
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 01MM2200, IMT-2000용 MPEG-4코덱 ASIC개발, 김익균
- 초록
- This paper presents an MPEG-4 video codec, called MoVa, for video coding applications that adopts 3G-324M. We designed MoVa to be optimal by embedding a cost-effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG-4 SP??2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. MoVa can be applied to many video systems requiring a high bit rate and various video formats, such as videophone, videoconferencing, surveillance, news, and entertainment.
- KSP 제안 키워드
- Bit Rate, Computational requirements, Discrete cosine Transform, Error Resilience(ER), Intra Refresh, MPEG-4 video, Motion Compensation(MoCo), Motion estimation(ME), Pipeline structure, Power Consumption, Rate Control
본 저작물은 공공누리 제4유형 : 출처표시 + 상업적 이용금지 + 변경금지 조건에 따라 이용할 수 있습니다.
