상세정보
학술지
A Platform-Based SoC Design of a 32-Bit Smart Card
- 발행일
- 200312
- 출처
- ETRI Journal, v.25 no.6, pp.510-516
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 02MB2100, 멀티미디어 이동통신 단말기용 고집적 시스템 IC 개발, 김종대
- 초록
- In this paper, we describe the development of a platform-based SoC of a 32-bit smart card. The smart card uses a 32-bit microprocessor for high performance and two cryptographic processors for high security. It supports both contact and contactless interfaces, which comply with ISO/IEC 7816 and 14496 Type B. It has a Java Card OS to support multiple applications. We modeled smart card readers with a foreign language interface for efficient verification of the smart card SoC. The SoC was implemented using 0.25 μm technology. To reduce the power consumption of the smart card SoC, we applied power optimization techniques, including clock gating. Experimental results show that the power consumption of the RSA and ECC cryptographic processors can be reduced by 32% and 62%, respectively, without increasing the area.
- KSP 제안 키워드
- Applied power, High performance, High security, Java card, Multiple Applications, Optimization techniques(OT), Platform-based, Power Consumption, Smart Card, SoC Design, clock gating