상세정보
학술지
Girth Conditioning for Construction of Short Block Length Irregular LDPC Codes
- 발행일
- 200402
- 출처
- Electronics Letters, v.40 no.3, pp.187-188
- ISSN
- 0013-5194
- 출판사
- IET
- 협약과제
- 04ZF1200, 정보통신 원천기술 연구, 정태형
- 초록
- A girth conditioning scheme for construction of short block length low-density parity-check (LDPC) codes is presented. The parity-check matrix is generated in a column-by-column fashion under the condition that a newly added column is chosen, among a number of trial columns, to maximise the average girth of variable nodes. The girth-conditioned LDPC codes are found to give a large performance gain especially at high SNRs.
- KSP 제안 키워드
- Block length, Irregular LDPC codes, Low density parity check (LDPC) code, Performance gain, Short Block, parity check matrix