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학술지 An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter
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저자
Byung-Do Yang, 최장홍, 한선호, Lee-Sup Kim, 유현규
발행일
200405
출처
IEEE Journal of Solid-State Circuits, v.39 no.5, pp.761-774
ISSN
0018-9200
출판사
IEEE
DOI
https://dx.doi.org/10.1109/JSSC.2004.826323
협약과제
03MB5100, 복합정보통신용 양방향 지상파 DMB 저전력 SoC 기술개발, 엄낙웅
초록
An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-μm CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm2. The spurious-free dynamic range (SFDR) is 55 dBc.
KSP 제안 키워드
3 V, 7 mm, 800 MHz, CMOS Process, Core area, D/A converter, Direct digital frequency synthesizer(DDFS), Low-Power, On-chip, Power Consumption, Quantization error