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Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver
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- Authors
- Kwang-Jin Koh, Mun-Yang Park, Cheon-Soo Kim, Hyun-Kyu Yu
- Issue Date
- 2004-06
- Citation
- IEEE Journal of Solid-State Circuits, v.39, no.6, pp.871-874
- ISSN
- 0018-9200
- Publisher
- IEEE
- Language
- English
- Type
- Journal Article
- Abstract
- Subharmonically pumped frequency down- and upconversion circuits are implemented in 0.18-/spl mu/m mixed-mode CMOS technology for 2-GHz direct-conversion WCDMA transceiver applications. These circuits operate in quadrature double-balanced mode and a required octet-phases (0/spl deg/, 45/spl deg/, 90/spl deg/, 135/spl deg/, 180/spl deg/, 225/spl deg/, 270/spl deg/, and 315/spl deg/) local oscillator (LO) signal comes from an active multiphases LO generator composed of a polyphase filter and active 45/spl deg/ phase shifting circuits. For linearity improvement, predistortion compensation and negative feedback schemes are used in the frequency down- and upconversion circuits, respectively. The downconverter achieves a conversion voltage gain of 20 dB (to 1-M/spl Omega/ load), 4-dBm IIP3 (18-dBm OIP3 to 50-/spl Omega/ load), 41-dBm IIP2 and 8.5-dB DSB NF at 1-MHz IF frequency, consuming 13.4 mA from 1.8-V supply, in the WCDMA Rx band (2110-2170 MHz). The upconverter, operating as two switched gain modes in the WCDMA Tx band (1920-1980 MHz), consumes 19.4 mA from 1.8-V supply and shows 14.5-dB conversion power gain, 15 -dBm OIP3 (0.5-dBm IIP3) and -11 dBm P/sub 1dB/ at maximum gain mode. At minimum gain mode, it realizes -0.3-dB conversion loss, 10.7-dBm OIP3 (11-dBm IIP3) and 0-dBm P/sub 1dB/, respectively. 3GPP WCDMA modulation tests are performed for both up- and downconversion circuits and the results are discussed in this paper.