상세정보
학술지
High-density Trench Gate DMOSFETs with Trench Contact Structure
- 발행일
- 200405
- 출처
- Electronics Letters, v.40 no.11, pp.699-700
- ISSN
- 0013-5194
- 출판사
- IET
- 협약과제
- 03MB5300, 나노소자기반 회로 설계기술 개발, 김종대
- 초록
- A novel process technique for fabricating trench gate DMOSFETs using the two-step trench technique and trench contact structure is realised to obtain higher cell density and lower on-resistance. Using this process technique, a remarkably increased trench gate DMOSFET with a cell pitch of 1.6 μm and a channel density of 130 Mcell/in2 are obtained. The fabricated device has a low specific on-resistance of 0.28 m廓 쨌 cm2 with a blocking voltage of 43 V, which is about 23 % lower than that of the device fabricated by the previous method.
- KSP 제안 키워드
- 3 V, Blocking voltage, Cell density, Channel Density, Contact structure, High-density, Novel process, Process technique, Two-Step, low specific on-resistance, trench gate