BROWSE
Detail
Journal Article
Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique
Cited 35 time in 
Share 
Share
- Authors
- Won-Ju Cho, Chang-Geun Ahn, Kiju Im, Jong-Heon Yang, Jihun Oh, In-Bok Baek, Seongjae Lee
- Issue Date
- 2004-06
- Citation
- IEEE Electron Device Letters, v.25, no.6, pp.366-368
- ISSN
- 0741-3106
- Publisher
- IEEE
- Language
- English
- Type
- Journal Article
- Abstract
- A novel plasma-doping technique for fabricating nanoscale silicon-on-insulator (SOI) MOSFETs has been investigated. The source/drain (S/D) extensions of the tri-gate structure SOI n-MOSFETs were formed by using an elevated temperature plasma-doping method. Even though the activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in a laterally abrupt S/D junction, we obtained a low sheet resistance of 920 廓/?뼞 by the elevated temperature plasma doping of 527°C. A tri-gate structure silicon-on-insulator n-MOSFET with a gate length of 50 nm was successfully fabricated and revealed suppressed short-channel effects.
- KSP Keywords
- Activation annealing, Doping method, Doping technique, Elevated temperatures, N-MOSFET, Plasma doping, Silicon On Insulator(SOI), gate length, low sheet resistance, short-channel effects, tri-gate