상세정보
학술지
Hybrid Multiplier for GF(2m) Defined by Some Irreducible Trinomials
- 발행일
- 200407
- 출처
- Electronics Letters, v.40 no.14, pp.852-853
- ISSN
- 0013-5194
- 출판사
- IET
- 협약과제
- 04SK1100, 차세대 시큐리티 기술 개발(나노 기술을 이용한 차세대 암호시스템 기술개발, 수학기반 암호기술 및 안전성, 조현숙
- 초록
- A trade-off between performance and area is important to design an efficient hardware structure for arithmetic operations in GF(2m). Proposed is a hybrid multiplier for GF(2m) with an irreducible trinomial, which can be constructed in variable structures depending on such a performance area trade-off.
- KSP 제안 키워드
- Arithmetic operations, Hybrid Multiplier, Trade-off, Variable structures, hardware structure