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Hybrid Multiplier for GF(2m) Defined by Some Irreducible Trinomials
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- Authors
- Y.J. Choi, K.-Y. Chang, D.W. Hong, H.S. Cho
- Issue Date
- 2004-07
- Citation
- Electronics Letters, v.40, no.14, pp.852-853
- ISSN
- 0013-5194
- Publisher
- IET
- Language
- English
- Type
- Journal Article
- Abstract
- A trade-off between performance and area is important to design an efficient hardware structure for arithmetic operations in GF(2m). Proposed is a hybrid multiplier for GF(2m) with an irreducible trinomial, which can be constructed in variable structures depending on such a performance area trade-off.
- KSP Keywords
- Arithmetic operations, Hybrid Multiplier, Trade-off, Variable structures, hardware structure