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Conference Paper
Design of the Clock Recovery Circuit with a Phase-Locked Loop for 40 Gb/s Optical Receivers
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- Authors
- Chan Ho Park, Dong Sik Woo, Kang Wook Kim, Sang-Kyu Lim
- Issue Date
- 2004-10
- Citation
- European Microwave Conference (EuMC) 2004, pp.757-759
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of a preamplifier, a nonlinear circuit with diodes, a bandpass filter and a clock amplifier. When a 40 Gb/s signal of 0 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -2 dBm output power. The implemented clock recovery circuit is to be used for the input of a phase-locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.
- KSP Keywords
- 40 Gb/s, Clock recovery(CR), Nonlinear circuit, Optical Receiver, Output power, bandpass filter(BFP), clock jitter, clock signal, phase-locked loop(PLL)