상세정보
학술지
A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer
- 저자
- 김진욱, 양정식, 변상진, Hyunduk Jun, 박정규, Cormac S. G. Conroy, 김범섭
- 발행일
- 200502
- 출처
- IEEE Journal of Solid-State Circuits, v.40 no.2, pp.462-471
- ISSN
- 0018-9200
- 출판사
- IEEE
- 협약과제
- 05MB3100, 초고속 유무선 네트워크용 SoC, 유현규
- 초록
- This paper presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5 Gb/s for a single 10-Gbit extended Attachment Unit Interface (XAUI) in a standard 0.18-μm CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than < 4.5 × 10-15 while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.
- KSP 제안 키워드
- Adaptive equalizer, Bit-error-rate(BER), CMOS Technology, Clock and Data Recovery, Four-Channel, Full-Duplex(FuDu), Least mean square(LMS), data rate, high-speed operation, low jitter, mixed-mode