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A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer
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- Authors
- Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S. G. Conroy, Beomsup Kim
- Issue Date
- 2005-02
- Citation
- IEEE Journal of Solid-State Circuits, v.40, no.2, pp.462-471
- ISSN
- 0018-9200
- Publisher
- IEEE
- Language
- English
- Type
- Journal Article
- Abstract
- This paper presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5 Gb/s for a single 10-Gbit extended Attachment Unit Interface (XAUI) in a standard 0.18-μm CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than < 4.5 × 10-15 while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.
- KSP Keywords
- Adaptive equalizer, Bit-error-rate(BER), CMOS Technology, Clock and Data Recovery, Four-Channel, Full-Duplex(FuDu), Least mean square(LMS), data rate, high-speed operation, low jitter, mixed-mode