상세정보
학술지
SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs
- 저자
- 박규설, 김상진, 백인복, Won-Hee Lee, Jong-Seuk Kang, 조용범, 이상돈, Chang-Keun Lee, 최정범, 김장한, Keun-Hyung Park, 조원주, 장문규, 이성재
- 발행일
- 200503
- 출처
- IEEE Transactions on Nanotechnology, v.4 no.2, pp.242-248
- ISSN
- 1536-125X
- 출판사
- IEEE
- 협약과제
- 05MF1200, 실리콘 미래 신소자 원천 기술개발, 이성재
- 초록
- We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios ?돧1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of ~2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13. © 2005 IEEE.
- KSP 제안 키워드
- Amplification ratio, Data analysis, E-beam Lithography, Field-effect transistors(FETs), Gate-controlled, High Voltage Gain, Logic Cell, Output Voltage, Pattern-dependent oxidation, Power amplification, Quantum limit