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학술대회 Implementation of a Phase-Locked Loop Clock Recovery Module for 40 Gb/s Optical Receivers
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저자
박찬호, 우동식, 김태규, 임상규, 김강욱
발행일
200506
출처
IEEE MTT-S International Microwave Symposium 2005, pp.2127-2130
DOI
https://dx.doi.org/10.1109/MWSYM.2005.1517168
협약과제
04MT1300, 40Gb/s급 시분할다중 광전송 기술, 고제수
초록
A low-cost, high-performance clock recovery (CR) module using a phase-locked loop (PLL) for 40 Gb/s optical receivers have been successfully designed and implemented. The recovered 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The timing jitter of the implemented PLL clock recovery module is significantly reduced as compared with the conventional open-loop type clock recovery module with a DR filter. The measured RMS jitter with the phase-locked CR module is about 250 fs. In addition, the CR module has been operated error-free during a 30-minute BER test with 40 Gb/s optical transceivers. © 2005 IEEE.
KSP 제안 키워드
10 Ghz, 40 gb/s, Clock recovery(CR), High performance, Low-cost, Optical receiver, Recovery module, open-loop, phase-locked loop(PLL), timing jitter