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Implementation of a Phase-Locked Loop Clock Recovery Module for 40 Gb/s Optical Receivers
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- Authors
- Chan Ho Park, Dong Sik Woo, Tae Gyu Kim, Sang Kyu Lim, Kang Wook Kim
- Issue Date
- 2005-06
- Citation
- IEEE MTT-S International Microwave Symposium 2005, pp.2127-2130
- Language
- English
- Type
- Conference Paper
- Abstract
- A low-cost, high-performance clock recovery (CR) module using a phase-locked loop (PLL) for 40 Gb/s optical receivers have been successfully designed and implemented. The recovered 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The timing jitter of the implemented PLL clock recovery module is significantly reduced as compared with the conventional open-loop type clock recovery module with a DR filter. The measured RMS jitter with the phase-locked CR module is about 250 fs. In addition, the CR module has been operated error-free during a 30-minute BER test with 40 Gb/s optical transceivers. © 2005 IEEE.
- KSP Keywords
- 10 Ghz, 40 gb/s, Clock recovery(CR), High performance, Low-cost, Optical receiver, Recovery module, open-loop, phase-locked loop(PLL), timing jitter