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Journal Article 30-nm recessed S/D SOI MOSFET with an ultrathin body and a low SDE resistance
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Authors
Chang-Geun Ahn, Won-Ju Cho, Kiju Im, Jong-Heon Yang, In-Bok Baek, Sungkweon Baek, Seongjae Lee
Issue Date
2005-07
Citation
IEEE Electron Device Letters, v.26, no.7, pp.486-488
ISSN
0741-3106
Publisher
IEEE
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.1109/LED.2005.851183
Abstract
A novel ultrathin body SOI MOSFET with a recessed source-drain (S/D) structure is proposed to reduce the S/D extension (SDE) resistance and the feasibility on the proposed device is checked. A recessed buried oxide under the SDE regions is completely filled with the heavily doped polysilicon, which can lead to a low SDE resistance. A recessed S/D SOI MOSFET with 30 nm gate length and 5 nm thick undoped channel, was successfully fabricated and showed the good SCE immunities; little punch-through, the drain-induced barrier lowering of 140 mV/V, and the subthreshold slope of 79 mV/dec. © 2005 IEEE.
KSP Keywords
5 nm, Buried oxide, Heavily doped, Punch-through, SOI MOSFET, Subthreshold slope(SS), drain-induced barrier lowering(DIBL), gate length, ultra-thin body(UTB), undoped channel