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Efficient pattern-based emulation for IEEE 802.11a baseband
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- Authors
- Il-Gu Lee, Heejung Yu, Sok-Kyu Lee, Jin Lee, Sin-Chong Park
- Issue Date
- 2005-07
- Citation
- International Workshop on System-on-Chip for Real-Time Applications (IWSOC) 2005, pp.1-4
- Language
- English
- Type
- Conference Paper
- Abstract
- As the design complexity and the number of gates per pin are increasing rapidly, functional verification has become a critical step in the development of a System-on-Chip (SoC). Traditional verification techniques, such as simulation or emulation, cannot satisfy the debugging requirement and simulation speed. Among various verification technologies, Pattern-Based emulation provides the most efficient execution speed, but has limited observability due to the limit on the number of available pins and memory size. In addition, it takes a long time to dump patterns into memory. We propose an efficient Pattern-Based emulation approach that combines a cycle-based simulation, an input pattern reduction method based on coverage result, and an automatic pattern comparing scheme. © 2005 IEEE.
- KSP Keywords
- Cycle-based simulation, Execution speed, Functional verification, IEEE 802.11a, Input pattern, Limited observability, Long Time, Memory size, Pattern Reduction, Pattern-based, Reduction method