상세정보
학술대회
Efficient pattern-based emulation for IEEE 802.11a baseband
- 저자
- 이일구, 유희정, 이석규, 이진, Sin-Chong Park
- 발행일
- 200507
- 출처
- International Workshop on System-on-Chip for Real-Time Applications (IWSOC) 2005, pp.1-4
- 협약과제
- 05MM1100, 4세대 이동통신 기술개발, 황승구
- 초록
- As the design complexity and the number of gates per pin are increasing rapidly, functional verification has become a critical step in the development of a System-on-Chip (SoC). Traditional verification techniques, such as simulation or emulation, cannot satisfy the debugging requirement and simulation speed. Among various verification technologies, Pattern-Based emulation provides the most efficient execution speed, but has limited observability due to the limit on the number of available pins and memory size. In addition, it takes a long time to dump patterns into memory. We propose an efficient Pattern-Based emulation approach that combines a cycle-based simulation, an input pattern reduction method based on coverage result, and an automatic pattern comparing scheme. © 2005 IEEE.
- KSP 제안 키워드
- Cycle-based simulation, Execution speed, Functional verification, IEEE 802.11a, Input pattern, Limited observability, Long Time, Memory size, Pattern Reduction, Pattern-based, Reduction method