상세정보
학술지
A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications
- 발행일
- 200508
- 출처
- IEEE Journal of Solid-State Circuits, v.40 no.8, pp.1671-1679
- ISSN
- 0018-9200
- 출판사
- IEEE
- 협약과제
- 04MB3600, 초고속 무선네트워크 SoC, 현석봉
- 초록
- A CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336 and 8.976 GHz in steps of 528 MHz and settles in approximately 150 ns is presented. The proposed PLL can be employed as a building block for a frequency synthesizer which generates a seven-band hopping carrier for multiband orthogonal frequency division multiplexing (MB-OFDM) ultrawideband (UWB) radio. To achieve fast loop settling, integer-N architecture that operates with 528-MHz reference frequency is implemented and a wideband active-loop filter is integrated. An improved phase-frequency detector (PFD) is proposed for faster loop settling. To reduce reference sidebands, a feedback circuit using replica bias is implemented in the charge pump. I/Q carriers are generated by two cross-coupled LC VCOs. The output current of the charge pump is controlled to compensate for the VCO gain nonlinearity and a programmable frequency divider (12 ?돞 N ?돞 17) that reliably operates at 9 GHz is designed. Fabricated in 0.18-μm CMOS technology, the PLL consumes 32 mA from a 1.8-V supply and achieves phase noise of -109.6 dBc/Hz at 1-MHz offset and spurs of -52 dBc. © 2005 IEEE.
- KSP 제안 키워드
- 6 GHz, Building block, CMOS Technology, Charge pump, Fast Settling, Feedback Circuit, Frequency synthesizer, MB-OFDM UWB, Multiband orthogonal frequency division multiplexing, Orthogonal frequency division Multiplexing(OFDM), Programmable Frequency Divider