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A 500MHz DLL with second order duty cycle corrector for low jitter
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- Authors
- Byung-Guk Kim, Kwang-Il Oh, Lee-Sup Kim, Dae-Woo Lee
- Issue Date
- 2005-09
- Citation
- Custom Integrated Circuits Conference (CICC) 2005, pp.325-328
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- A DLL with a second order duty cycle corrector which consists of a low pass filter and an integrator is presented. This paper shows the analysis and the design of the second order DCC for loop stability and low jitter. The DLL implemented in a 0.13μm CMOS process achieves an output duty error below 짹1.6% within 짹25% external input duty error. It has a 29.2ps peak-to-peak jitter and a 3.8ps RMS jitter. ©2005 IEEE.
- KSP Keywords
- CMOS Process, Duty cycle(DC), External input, Loop stability, Low jitter, Low pass filter(LPF), duty cycle corrector, second-order