상세정보
학술대회
A 500MHz DLL with second order duty cycle corrector for low jitter
- 저자
- Byung-Guk Kim, 오광일, Lee-Sup Kim, 이대우
- 발행일
- 200509
- 출처
- Custom Integrated Circuits Conference (CICC) 2005, pp.325-328
- 협약과제
- 05MB1100, 나노소자기반 회로 설계기술 개발, 김종대
- 초록
- A DLL with a second order duty cycle corrector which consists of a low pass filter and an integrator is presented. This paper shows the analysis and the design of the second order DCC for loop stability and low jitter. The DLL implemented in a 0.13μm CMOS process achieves an output duty error below 짹1.6% within 짹25% external input duty error. It has a 29.2ps peak-to-peak jitter and a 3.8ps RMS jitter. ©2005 IEEE.
- KSP 제안 키워드
- CMOS Process, Duty cycle(DC), External input, duty cycle corrector, loop stability, low jitter, lowpass filter, second-order