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Conference Paper Face Recognition HW/SW IP implementation and validation for high reliability using a Virtual Platform
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Authors
Miyoung Lee, Hyuk Kim, Youngseok Baek, Seongmin Kim, Bontae Koo, Joohyun Lee
Issue Date
2015-06
Citation
International Symposium on Consumer Electronics (ISCE) 2015, pp.1-2
Publisher
IEEE
Language
English
Type
Conference Paper
DOI
https://dx.doi.org/10.1109/ISCE.2015.7177817
Project Code
15MS3100, The Core Technology Development of SW-SoC Convergence Platform for Hyper-Connection Services among Smart Devices based on Heterogeneous Multi-core C, Lim Chae Deok
Abstract
This paper presents design details of a Virtual Platform (VP) which is used for developing real time hardwired face recognition system. VP is promising technology to develop complex HW/SW system because it enables the simultaneous development of hardware and software. We have implemented a Virtual Platform and we used it for developing FPGA based face recognition system. The hardware portion is modeled with Transaction Level Model (TLM) in early phase of development. After hardware have been implemented, TLM model is substituted with real hardware system. The software is simultaneously developed with TLM hardware model and SW/HW integrity verification is seamlessly done by substituting TLM model with FPGA based real hardware. TLM model was efficient because it was much faster than RTL model and it can be seamlessly interfaced with SW development environment of virtual platform. FPGA based face recognition system was fully verified using application software running on virtual platform.
KSP Keywords
Application Software, Development environment, Face recognition systems, Hardware model, High Reliability, Integrity verification, Real-Time, Transaction Level Model, Virtual platform, hardware and software, hardware system