상세정보
학술지
Design and Architecture of Low-Latency High-Speed Turbo Decoders
- 발행일
- 200510
- 출처
- ETRI Journal, v.27 no.5, pp.525-532
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 05MR2700, 광대역 적응형 위성통신방송 융합기술 개발, 오덕길
- 초록
- In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.
- KSP 제안 키워드
- Bit Error Rate(And BER), Bit Error Rate performance, Communication services, Conventional methods, Correction scheme, Field Programmable Gate Arrays(FPGA), Forward error correction(FEC), High Speed, Iterative Decoding, Low latency, Radix-4