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Journal Article
Design and Architecture of Low-Latency High-Speed Turbo Decoders
- Authors
- Ji Won Jung, In Ki Lee, Duk Gun Choi, Jin Hee Jeong, Ki Man Kim, Eun A Choi, Deock Gil Oh
- Issue Date
- 2005-10
- Citation
- ETRI Journal, v.27, no.5, pp.525-532
- ISSN
- 1225-6463
- Publisher
- 한국전자통신연구원 (ETRI)
- Language
- English
- Type
- Journal Article
- Abstract
- In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.
- KSP Keywords
- Bit Error Rate performance, Communication services, Conventional methods, Correction scheme, Field-Programmable Gate Array(FPGA), Forward Error Correction(FEC), High Speed, Latency reduction, Low latency, Radix-4, Real-time