본 논문은 IEEE802.15.3a Alt-PHY로 표준화중인 MB-OFDM UWB(Multi-Band Orthogonal Frequency Division Multiplexing Ultra Wide Band) 시스템 수신기 설계 방안을 제시하고 링크 마진(link margin) 설계를 위해 4 병렬 구조에 의한 구현 손실을 정량적으로 분석하는 것이다. 먼저 MB-OFDM UWB 시스템의 전송 방식을 설명하고, 동기 구조를 완전한 디지털 방식으로 설계하기 위해 반송 주파수 옵셋(carrier frequency offset)과 샘플링 클락 옵셋(sampling clock offset)이 MB-OFDM UWB 시스템에 미치는 영향을 분석하였다. 그리고 이러한 반송 주파수 옵셋과 샘플링 클락 옵셋을 추정하고 보상하기 위한 알고리즘과 VLSI 구현을 위하여 MB-OFDM UWB 시스템의 패킷 전송 구조를 이용한 4 병렬 동기 구조를 제시하였다. 본 논문에서 제시한 시스템 동기를 위한 수신 구조와 단순화된 4 병렬 구조에 의한 구현 손실 값은 MB-OFDM 시스템 규격에서 제시한 최대 허용 가능한 반송 주파수 옵셋 및 샘플링 클락 옵셋에서 최대 3.08 dB로 시뮬레이션을 통해 분석되었다.
KSP Keywords
Carrier Frequency Offset, Clock offset, Link Margin, MB-OFDM UWB, Orthogonal Frequency-Division Multiplexing(OFDM), Sampling clock, Ultra wide band(UWB), multi-band
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