상세정보
학술지
Strain Relaxed SiGe Buffer Prepared by Means of Thermally Driven Relaxation and CMP
- 발행일
- 200511
- 출처
- Electrochemical and Solid-State Letters, v.8 no.11, pp.G304-G306
- ISSN
- 1099-0062
- 출판사
- Electrochemical Society (ECS)
- 협약과제
- 05MB3400, H/W로 재구성 가능한 차세대 지능형 통합단말용 SoC(차세대 통합 휴대 단말 기술), 조경익
- 초록
- In this paper, we propose a new concept of thin SiGe virtual substrates in which the intermediate in situ annealing steps during graded SiGe layer growth play a key role. This annealing step increases misfit dislocation flow and relaxes the graded SiGe layer with a relaxation of 97.8%. Using thermally driven relaxation (TDR), it is possible to control the strain relief and the propagation of threading dislocations (IDs) to the top of buffer layers. In addition TDR, chemical mechanical polishing (CMP) helps to reduce surface roughness comparable to Si wafer. The regrowth of Si0.8Ge 0.2 layer on the polished Si0.8Ge0.2 buffer was found to keep its surface roughness and TD density. Optimized 1 μm thick Si0.8Ge0.2 buffer exhibited ~ 1 nm of surface roughness and threading dislocation density was less than 4 × 10 5/cm2. © 2005 The Electrochemical Society. rights reserved.
- KSP 제안 키워드
- Buffer layer, Chemical Mechanical Polishing(CMP), In-situ annealing, Key role, Layer growth, Misfit dislocation, Polished Si, Relaxed SiGe, Si wafer, SiGe virtual substrates, Surface roughness