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Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation
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- Authors
- Ku-Young Chang, Dowon Hong, Hyun-Sook Cho
- Issue Date
- 2005-12
- Citation
- IEEE Transactions on Computers, v.54, no.12, pp.1628-1630
- ISSN
- 0018-9340
- Publisher
- IEEE
- Language
- English
- Type
- Journal Article
- Abstract
- This paper presents a new bit-parallel multiplier for the finite field GF(2m) defined by an irreducible all-one polynomial. In order to reduce the complexity of the multiplier, we introduce a redundant representation and use the well-known multiplication method proposed by Karatsuba. The main idea is to combine the redundant representation and the Karatsuba method to design an efficient bit-parallel multiplier. As a result, the proposed multiplier requires about 25 percent fewer AND/ XOR gates than the previously proposed multipliers using an all-one polynomial, while it has almost the same time delay as the previously proposed ones. © 2005 IEEE.
- KSP Keywords
- All-one polynomials, Bit-parallel multiplier, Finite field GF(2n), Karatsuba method, Time Delay, low-complexity, redundant representation