상세정보
학술지
Low complexity bit-parallel multiplier for GF(2/sup m/) defined by all-one polynomials using redundant representation
- 발행일
- 200512
- 출처
- IEEE Transactions on Computers, v.54 no.12, pp.1628-1630
- ISSN
- 0018-9340
- 출판사
- IEEE
- 협약과제
- 05MK2500, 차세대 시큐리티 기술 개발, 조현숙
- 초록
- This paper presents a new bit-parallel multiplier for the finite field GF(2m) defined by an irreducible all-one polynomial. In order to reduce the complexity of the multiplier, we introduce a redundant representation and use the well-known multiplication method proposed by Karatsuba. The main idea is to combine the redundant representation and the Karatsuba method to design an efficient bit-parallel multiplier. As a result, the proposed multiplier requires about 25 percent fewer AND/ XOR gates than the previously proposed multipliers using an all-one polynomial, while it has almost the same time delay as the previously proposed ones. © 2005 IEEE.
- KSP 제안 키워드
- All-one polynomials, Bit-parallel multiplier, Finite field GF(2n), Karatsuba method, Time Delay, low-complexity, redundant representation