상세정보
학술대회
A Novel CMOS Down-Conversion Mixer with Current Reuse Technique
- 발행일
- 200512
- 출처
- Asia-Pacific Microwave Conference (APMC) 2005, pp.1-4
- 협약과제
- 05MB2900, 초저전력 RF/HW/SW 통합 SoC, 박성수
- 초록
- A novel low voltage and power mixer topology for 5GHz wireless LAN applications is presented in this paper. To reduce power dissipation, a novel mixer topology with a low supply voltage and using the current reuse technique is designed using a 0.18 μm CMOS process. The designed down-conversion mixer has a conversion gain of 7.5dB, a P1dB of -16Bm and an HP3 of -6dBm, respectively, with LO power of -7dBm while consuming 1.6mA under a 1.5V supply voltage. The chip size including pads is 0.77mm × 0.81mm. © 2005 IEEE.
- KSP 제안 키워드
- CMOS Process, Conversion gain, Down-conversion mixer, LO power, Low Supply Voltage, Wireless Local Area Networks(WLANs), current reuse, low voltage, power dissIPation