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Conference Paper EBL Patterning of Sub-10 nm Line Using HSQ with Plasma Etching Process and Fabricating of Triple-Gate MOS Transistors with 6 nm Gate Length
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Authors
I.B. Baek, J.H. Yang, W.J. Cho, C.G. Ahn, K.J. Im, S.J. Lee
Issue Date
2005-06
Citation
Silicon Nanoelectronics Workshop (SNW) 2005, pp.16-17
Language
English
Type
Conference Paper
KSP Keywords
Plasma etching process, Sub-10 nm, Triple-gate, gate length