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Journal Article
Accelerating Verification with Reusable Testbench
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- Authors
- Jung Ho Son, Hae Wook Choi, Sin Chong Park
- Issue Date
- 2006-02
- Citation
- IEICE Transactions on Information and Systems, v.E89-D, no.2, pp.853-856
- ISSN
- 0916-8532
- Publisher
- 일본, 전자정보통신학회 (IEICE)
- Language
- English
- Type
- Journal Article
- Project Code
- 05MM1100, Research on 4G Mobile Communications Technology, Hwang Seung Ku
- Abstract
- The increased complexity in system design has brought an explosive growth in functional verification time. Thus, many verification methodologies have been proposed to reduce it. One of them is the co-emulation method in which the hardware accelerator and software simulator work together. This paper presents an effective testbench architecture for accelerated verification and reuse of parts of the testbench in co-emulation. The testbench is divided into a synthesizable part which can be hardware accelerated and a non-synthesizable part which remains on the software simulator. The split blocks of the testbench can be reused in other test environments. Experiments with real world systems show that the proposed verification environment has over 31% higher performance than that of the conventional co-emulation environment. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.
- KSP Keywords
- Emulation environment, Functional verification, Hardware accelerator, Higher performance, Information and communication, Real-world, Verification Environment, software simulator, system design