상세정보
학술지
Accelerating Verification with Reusable Testbench
- 저자
- 손정보, 최해욱, 박신종
- 발행일
- 200602
- 출처
- IEICE Transactions on Information and Systems, v.E89-D no.2, pp.853-856
- ISSN
- 0916-8532
- 출판사
- 일본, 전자정보통신학회 (IEICE)
- 협약과제
- 05MM1100, 4세대 이동통신 기술개발, 황승구
- 초록
- The increased complexity in system design has brought an explosive growth in functional verification time. Thus, many verification methodologies have been proposed to reduce it. One of them is the co-emulation method in which the hardware accelerator and software simulator work together. This paper presents an effective testbench architecture for accelerated verification and reuse of parts of the testbench in co-emulation. The testbench is divided into a synthesizable part which can be hardware accelerated and a non-synthesizable part which remains on the software simulator. The split blocks of the testbench can be reused in other test environments. Experiments with real world systems show that the proposed verification environment has over 31% higher performance than that of the conventional co-emulation environment. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.
- KSP 제안 키워드
- Emulation environment, Functional verification, Hardware accelerator, Higher performance, Information and communication, Real-world, Verification Environment, software simulator, system design