상세정보
학술지
Implementation of a Low-Cost Phase-Locked Loop Clock-Recovery Module for 40-Gb/s Optical Receivers
- 발행일
- 200602
- 출처
- Microwave and Optical Technology Letters, v.48 no.2, pp.312-315
- ISSN
- 0895-2477
- 출판사
- John Wiley & Sons
- 협약과제
- 05MT1500, 40Gb/s급 시분할다중 광전송 기술(40Gb/s 고속 광링크 기술 연구), 고제수
- 초록
- A low-cost, compact, high-performance clock-recovery (CR) module using a new phase-locked loop (PLL) for 40-Gb/s optical receivers is successfully designed and implemented. The newly implemented frequency detector in the PLL helps to reduce the current consumption and also extended the frequency-capture range. The implemented PLL clock-recovery module demonstrates advantages over the conventional open-loop type clock-recovery module with a DR filter by significantly improving clock jitter, thus reducing overall module cost, and allowing the possibility of providing a proper clock signal in the case of temporary loss of NRZ input signals. The CR module exhibits error-free operation during a 30-min BER test with a time-division-multiplexing (TDM) 40-Gb/s transmission system. © 2005 Wiley Periodicals, Inc.
- KSP 제안 키워드
- Capture range, Current consumption, High performance, Low-cost, Optical receiver, Phase locked loop(PLL), Recovery module, Time division multiplexing, Transmission system, clock jitter, clock signal