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Conference Paper
Design and Performance Analysis of HomePNA 2.0 Transceiver Chip Circuit
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- Authors
- Jong Won Kim, Jae Doo Huh, Dae Young Kim
- Issue Date
- 2006-02
- Citation
- International Conference on Advanced Communication Technology (ICACT) 2006, pp.1702-1705
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- In this paper, we present the architecture of Home Phoneline Networking Alliance (HomePNA) 2.0 transceiver chip circuit which can establish a home network using existing in-home phone line, and it provides a data rate of 4 - 32 Mbps. We evaluate the performance of HomePNA 2.0 transceiver chip by running a simulation to study Mean Squared Error (MSE), eye diagram and constellation. By analyzing the results of each simulation, we also analyze the performance of HomePNA 2.0 transceiver chip in a comprehensive manner.
- KSP Keywords
- Eye Diagram, Home Network, Performance analysis, Transceiver chip, chip circuit, data rate, mean square error(MSE)