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학술대회
Design and Performance Analysis of HomePNA 2.0 Transceiver Chip Circuit
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- 발행일
- 200602
- 출처
- International Conference on Advanced Communication Technology (ICACT) 2006, pp.1702-1705
- 협약과제
- 05MH2500, 무선 홈네트워크 기반 HD급 대화형 멀티미디어 서비스 기술개발, 김채규
- 초록
- In this paper, we present the architecture of Home Phoneline Networking Alliance (HomePNA) 2.0 transceiver chip circuit which can establish a home network using existing in-home phone line, and it provides a data rate of 4 - 32 Mbps. We evaluate the performance of HomePNA 2.0 transceiver chip by running a simulation to study Mean Squared Error (MSE), eye diagram and constellation. By analyzing the results of each simulation, we also analyze the performance of HomePNA 2.0 transceiver chip in a comprehensive manner.
- KSP 제안 키워드
- Eye Diagram, Home Network, Performance analysis, Transceiver chip, chip circuit, data rate, mean square error(MSE)