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Conference Paper
A 40-360 MHz Low-Power CMOS Frequency Synthesizer With Improved Multimodulus Prescaler
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- Authors
- Ja Yol Lee, Kwi Dong Kim, Jong Kee Kwon, Jong Dae Kim, Sang Heung Lee
- Issue Date
- 2006-02
- Citation
- 한국반도체 학술 대회 (KCS) 2006, pp.1-2
- Publisher
- 대한전기학회
- Language
- English
- Type
- Conference Paper
- Abstract
- In this paper, we present a low-power CMOS frequency synthesizer using phase-locked loop. In the frequency synthesizer, an improved programmable multimodulus divider is implemented.The multimodulus divider generates 30 numbers of divide ratios, contains less control logics, and therefore consumes less power.The frequency synthesizer generates from 40MHz to 360MHz locked signal. The phase noise is -133 dBc/Hz at 10 MHz from 167.375 MHz, and the power consumption is 6mW at 1.2V. The active chip area is 350µm × 380µm. The frequency synthesizer is fabricated using 130nm CMOS process with 8 metal layers.
- KSP Keywords
- CMOS Process, Chip area, Frequency synthesizer, Power Consumption, low-power CMOS, metal layer, phase noise, phase-locked loop(PLL)