상세정보
학술지
Characterization of Silicon-Germanium Heterojunction Bipolar Transistor Degradation in Silicon-Germanium BiCMOS Technology
- 발행일
- 200603
- 출처
- Solid-State Electronics, v.50 no.3, pp.333-339
- ISSN
- 0038-1101
- 출판사
- Elsevier
- 협약과제
- 05MB1200, 나노급 상변화 정보저장기술 개발, 유병곤
- 초록
- The degradations of SiGe heterojunction bipolar transistors (HBTs) caused by the integration of the HBTs with a CMOS process were investigated. SiGe HBTs were fabricated using two sorts of BiCMOS technology, the HBT-during-CMOS (HDC) process by which SiGe HBTs and Si CMOS transistors are generated simultaneously, and the HBT-after-CMOS (HAC) process whereby SiGe HBTs are prepared after the CMOS element formation. While the current gain, the cut-off frequency (ft), and the maximum oscillation frequency (fmax) decreased by the HDC process, the SiGe HBTs prepared by the HAC process exhibited lower fmax and breakdown voltage than the control HBTs made by a SiGe HBT process. These specific deteriorations originated from the doping concentration variations in the SiGe base for the HDC process and in the surface of collector for the HAC process, respectively. The thermal heat of the source-drain anneal broadened the boron profile in the SiGe base and induced the location change of emitter-base and collector-base junctions in the HDC process. The surface concentration of the collector increased due to the phosphorus evaporated from the gate poly-silicon during the HAC process. The device performances could be improved to the level of the control HBTs by modifying the BiCMOS processes either by decreasing the source-drain anneal temperature to suppress the boron diffusion or overlaying capping layers on the gate poly-silicon to prevent the auto-doping. © 2006 Elsevier Ltd. All rights reserved.
- KSP 제안 키워드
- Anneal temperature, BiCMOS Technology, Breakdown voltage(BDV), CMOS Process, Capping layer, Current Gain, Cut-off frequency, Doping concentration, Heterojunction Bipolar Transistors(HBTs), Poly-silicon, Si CMOS