상세정보
학술지
A Gigabit Link CMOS Analog Interface for High Performance Signaling
- 저자
- 박성경
- 발행일
- 200604
- 출처
- Analog Integrated Circuits and Signal Processing, v.47 no.1, pp.5-12
- ISSN
- 0925-1030
- 출판사
- Springer
- 협약과제
- 05MB3100, 초고속 유무선 네트워크용 SoC, 유현규
- 초록
- In this brief, design of a gigabit link CMOS analog interface composed of a transmitter, a receiver, and clocking circuits is addressed with focus on high-performance signaling in terms of interference and jitter. The low-cost, low-power interface is targeted at parallel link applications. The transmitter adopts one-tap preemphasis to mitigate the intersymbol interference (ISI) problem. The receiver samples two adjacent bits and stores the difference of them to a capacitor, so it is more immune to timing uncertainties caused by nonideal sampling clocks and it is dependent only on the direction or difference of two consecutive bits, not on the absolute values of them. With these circuits, robust clocking circuits to multiplex and demultiplex the data on the transmit and receive side, respectively, are designed. Pseudo-differential-type delay elements are used in the oscillator and delay line to enable high power supply rejection ratio and low jitter. The delay locked loop (DLL) is designed to prevent harmonic locking. The transceiver performance is tested at 1 Gbps and 2 Gbps for double and quadruple interleaving, respectively. The maximum operating speed is about 1.7 Gbps for double interleaving and about 3 Gbps for the quadruple-interleaving receiver under a 3.3 V, 0.35 μm CMOS process. © 2006 Springer Science + Business Media. Inc.
- KSP 제안 키워드
- 3 V, CMOS Process, Delay elements, Delay-Locked Loop, High performance, Inter-Symbol-Interference(ISI), Low-Power, Low-cost, Operating speed, Parallel link, Power interface