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Conference Paper
Efficient Stereo Matching by Dropping Disparity Levels for FPGA Implementation
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- Authors
- Jiho Chang, Jae-chan Jeong
- Issue Date
- 2015-07
- Citation
- International Conference on Machine Vision and Machine Learning (MVML) 2015, pp.1-5
- Language
- English
- Type
- Conference Paper
- Abstract
- Stereo matching is a traditional method used to obtain three-dimensional depth information and has been studied for decades. However, it is still difficult to apply stereo matching algorithms to real-time systems because of its heavy computation requirements. A stereo matching implementation of an FPGA system with high-resolution images uses a significant amount of logic and memory. When implementing stereo matching in FPGA, factors that determine the size of logic and memory required are the resolution of the images and the disparity levels. In this paper, we present a spare cost computation method to implement a stereo matching system on FPGA by dropping disparity levels. In addition, using a subpixel estimation and filtering method to calculate the dropped disparity levels, we present an effective method to regenerate the costs. In addition, the performance and resource usage of the proposed method is compared with that of conventional methods.
- KSP Keywords
- Computation method, Conventional methods, Cost Computation, Depth information, FPGA Implementation, Filtering method, High resolution images, Matching System, Real-Time Systems, Resource Usage, Stereo matching algorithms