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Maximizing the Spectral efficiency of OFDMA System over Fast Fading channels
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- Authors
- Kee Young Shin, Kang Yong Lee, Kwang Yong Lee, Pyeong Soo Mah, Seung Min Park, Heung Nam Kim
- Issue Date
- 2006-05
- Citation
- Vehicular Technology Conference (VTC) 2006 (Spring), pp.1027-1032
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- Time synchronization for Embedded Sensor Networks (ESN) is important for accurate time stamping of events and fine-tuned coordination of duty cycles to minimize power consumption. This paper presents a novel Chained-RIpple Time Synchronization (CRIT) protocol that is fast, flexible, and high-precise in ESN. CRIT adopts hierarchical and multi-hop time synchronization architecture with supporting energy-saving problem in ESN. The algorithm works in two phases. In the first phase, a horizontal structure between Missionary Nodes (MN) is established in the network by Piggy-Back Neighbor Time Synchronization (PBNT) algorithm. In the second phase, a vertical structure between a MN and Sensor Nodes (SN) is set up in each sensor group (SG) by Distributed Depth First Search (DDFS) algorithm. By applying these two phases repeatedly, all nodes in ESN efficiently synchronize to each other. For the purpose of performance evaluation, we first study the error sources of CRIT. In addition, we simulate CRIT in terms of synchronization errors of two phases and clock offset using network simulator (NS-2). The simulation results show that CRIT provides very accurate time synchronization and it can be easily expanded to real ESN. © 2006 IEEE.
- KSP Keywords
- Clock offset, Depth-First search, Duty cycle(DC), Embedded sensor, Energy saving, Error source, Multi-Hop, Network simulator(NS), Network simulator-2(NS2), Performance evaluation, Power Consumption