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A 1 .25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution
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- Authors
- Chang Kyung Seong, Seung Woo Lee, Woo Young Choi
- Issue Date
- 2006-05
- Citation
- International Symposium on Circuits and Systems (ISCAS) 2006, pp.2113-2116
- Language
- English
- Type
- Conference Paper
- Project Code
- 06MT2300, 멀티서비스 스위치 개발, Lee Bhum Cheol
- Abstract
- This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 μm CMOS technology. In the measurement, the CDR has 짹400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 μm × 165 μm. © 2006 IEEE.
- KSP Keywords
- CMOS Technology, Chip area, Clock and Data Recovery Circuit(CDR), Digitally controlled, Dual-loop, Frequency offset tolerance, Offset tolerance(OT), Phase resolution, Power Consumption, Reference clock, delay buffer