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An Low Complexity Hardware Implementation of MIMO Detector with Application to WLAN
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- Authors
- Chan Ho Yoon, Eun Young Choi, Jung Bo Son, Sok Kyu Lee, Tae Hyun Jeon
- Issue Date
- 2006-05
- Citation
- Vehicular Technology Conference (VTC) 2006 (Spring), pp.2271-2275
- Language
- English
- Type
- Conference Paper
- Project Code
- 06MM2400, Development of IEEE 802.11n Modem & RF Chip-sets with Data Rate 200Mbps, Sok-Kyu Lee
- Abstract
- In this paper, we describe a FPGA implementation of MI MO detector for future wireless communication system with application to wireless LAN, targeted for upcoming 802.11n standard. The MIMO detector assumes 2 transmit and 3 receive antennas. In soft-output demapper, we apply channel state information which effectively weights reliability information to soft-decision output bits for enhanced link-level performance. The implementation complexity is significantly reduced by avoiding repeated pseudo-inverse calculation for interference cancellation of every received symbol vector. Furthermore, the overall processing time and fabrication area it takes can be significantly reduced by applying bit reduction technique. © 2006 IEEE.
- KSP Keywords
- 802.11n standard, Channel State Information(CSI), FPGA Implementation, Hardware Implementation, Implementation complexity, Interference cancellation, Inverse calculation, MIMO detector, Pseudo-inverse, Reduction technique, Reliability information