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Low Power Implementation of SHA-1 Algorithm for RFID System
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- 발행일
- 200606
- 출처
- International Symposium on Consumer Electronics (ISCE) 2006, pp.682-686
- 협약과제
- 06MK1700, 안전한 RFID/USN을 위한 정보보호 기술 개발, 정교일
- 초록
- In this paper, we implemented the low power and small area hardware of SHA-1 hash function for RFID tag. For small area design we optimized operation logics and for low power design we minimized data transitions of register memory. It is implemented with 10,641 gates at Samsung 0.25μm CMOS technology and it needs 330 operation clocks for one hash function of 160-bit data. Its power consumption is 19.5uW at 100kHz operation clock1. © 2006 IEEE.
- KSP 제안 키워드
- CMOS Technology, Hash Function, Low-Power design, Optimized operation, Power Consumption, RFID Tag, RFID system, SHA-1, low power Implementation, low power and small area