상세정보
학술대회
Performance Improvement of a 40 Gb/s PLL Clock Recovery Module Using New Frequency Acquisition and Clock Hold Circuits
- 저자
- 박현, 우동식, 김진중, 임상규, 김강욱
- 발행일
- 200606
- 출처
- IEEE MTT-S International Microwave Symposium Digest 2006, pp.494-497
- 협약과제
- 05MT1500, 40Gb/s급 시분할다중 광전송 기술(40Gb/s 고속 광링크 기술 연구), 고제수
- 초록
- Significant performance improvements have been obtained with a 40 Gb/s phase-locked clock recovery (CR) module for fiber optic receivers by employing a new frequency acquisition circuit in the phase-locked loop (PLL) and a clock hold circuit. The new simple frequency acquisition circuit helps to extend the frequency lock-range, obtain faster frequency acquisition, and reduce the current consumption as compared with the conventional ones. In addition, a clock hold circuit helps to prevent the loss of the clock signal in the cases of temporary input signal loss. The measured RMS jitter of the improved PLL CR module at 40 Gb/s is about 250 fs, which is significantly better than the open-loop type CR module. © 2006 IEEE.
- KSP 제안 키워드
- 40 gb/s, Clock recovery(CR), Current consumption, Fiber optic, Frequency lock, Input signal, Recovery module, S phase, Signal loss, clock signal, frequency acquisition