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Design a Switch Wrapper for SNA On-Chip-Network
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- Authors
- Ji Ho Chang, Jong Su Yi, Jun Seong Kim
- Issue Date
- 2006-06
- Citation
- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E89-A, no.6, pp.1615-1621
- ISSN
- 1745-1337
- Publisher
- 일본, 전자정보통신학회 (IEICE)
- Language
- English
- Type
- Journal Article
- Abstract
- In this paper we present a design of a switch wrapper as a component of SNA (SoC Network Architecture), which is an efficient on-chip-network compared to a shared bus architecture in a SoC. The SNA uses crossbar routers to provide the increasing demand on communication bandwidth within a single chip. A switch wrapper for SNA is located between a crossbar router and IPs connecting them together. It carries out a mode of routing to assist crossbar routers and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, two AHB-SNP converters, a controller and two optional interface socket modules. We implemented a SNP switch wrapper in VHDL and confirmed its functionality using ModelDim simulation. Also, we synthesized it using a Xilinx Virtex2 device to determine resource requirements: the switch wrapper seems to occupy appropriate spaces, about 900 gates, considering that a single SNA crossbar router costs about 20,000 gates. copyright © 2006 The Institute of Electronics, Information and Communication Engineers.