상세정보
학술지
A 10-bit 400-MS/s 160-mW 0.13-μm CMOS dual-Channel Pipeline ADC without Channel Mismatch Calibration
- 발행일
- 200607
- 출처
- IEEE Journal of Solid-State Circuits, v.41 no.7, pp.1596-1605
- ISSN
- 0018-9200
- 출판사
- IEEE
- 협약과제
- 06MB1100, 나노소자기반 회로 설계기술 개발, 김종대
- 초록
- This paper describes a 10-bit 400-MS/s dual-channel analog-to-digital converter (ADC) insensitive to offset, gain, and sampling-time mismatches between channels. An adaptive closed-loop sampling technique based on a multi-stage amplifier eliminates the channel offset effectively. Multi-stage amplifiers with high DC gain reduce the gain mismatch between channels and guarantee a large signal swing at low supply voltages. A single clock-edge sampling scheme for clock-skew reduction minimizes the sampling-time mismatch. The proposed prototype ADC in a 0.13-μm CMOS process occupies an active area of 4.2 mm 2, dissipates 160 m W from 1.2 V and 400 MS/s, and shows a signal-to-noise-and-distortion ratio of 54.8 dB with a 29-MHz sinusoidal input at 400 MS/s without any channel-mismatch calibration technique. The measured maximum offset and gain mismatches are less than 0.1% and 0.2%, respectively. © 2006 IEEE.
- KSP 제안 키워드
- 2 mm, Active area, Analog to digital converter(ADC), CMOS Process, Closed-loop, DC gain, Distortion ratio, Edge sampling, Pipeline ADC, Sampling scheme, Signal-to-Noise-and-Distortion