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Conference Paper
Low Jitter 1.56GHz PLL Clock Generator for 3.125Gb/s/ch CMOS Serial Link Transceiver
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- Authors
- Sang Jin Byun, Cheon Soo Kim
- Issue Date
- 2006-07
- Citation
- International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2006, pp.75-768
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- KSP Keywords
- clock generator, low jitter, serial link