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Clock and Data Recovery Circuit Using Digital Phase Aligner and Phase Interpolator
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- Authors
- Seung Woo Lee, Chang Kyung Seong, Woo Young Choi, Bhum Cheol Lee
- Issue Date
- 2006-08
- Citation
- Midwest Symposium on Circuits and Systems (MWSCAS) 2006, pp.690-693
- Language
- English
- Type
- Conference Paper
- Abstract
- Clock and data recovery circuit using digital phase aligner and phase interpolator is proposed for multi-channel link applications. The proposed circuit reduces recovered clock jitter and alleviates the problem of distorted clock duty cycle. It is realized in 0.13um CMOS technology. Its power dissipation is 9.7mW at 1.2V power supply and its occupation area is 290×230um2 with multi-phase dock generation block. The experimental results show that the proposed circuit recovers 1Gb/s of 2 7-1 FRBS with no error. © 2006 IEEE.
- KSP Keywords
- CMOS Technology, Clock and Data Recovery Circuit(CDR), Duty cycle(DC), clock jitter, multi-channel, multi-phase, phase interpolator, power dissIPation, power supply