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Journal Article Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis
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Authors
Sun Mi Park, Ku Young Chang, Do Won Hong
Issue Date
2006-09
Citation
IEEE Transactions on Computers, v.55, no.9, pp.1211-1215
ISSN
0018-9340
Publisher
IEEE
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.1109/TC.2006.146
Abstract
In this paper, we present a bit-parallel multiplier for GF(2m) defined by an irreducible pentanomial xm + xk3 + xk2 + xk1 + 1, where 1 ?돞 k1 < k2 < k3 ?돞 m/2. In order to design an efficient bit-parallel multiplier, we introduce a shifted polynomial basis and modify a reduction matrix presented by Reyhani-Masoleh and Hasan. As a result, the time complexity of the proposed multiplier is TA + (3+ ?뙂log2(m - 1)?뙃)TX, where TA and TX are the delay of one AND and one XOR gate, respectively. This result matches or outperforms the previously known results. On the other hand, the proposed multiplier has the same space complexity as the previously known multipliers except for special types of irreducible pentanomials. Note that its hardware architecture is similar to that presented by Reyhani-Masoleh and Hasan. © 2006 IEEE.
KSP Keywords
Bit-parallel multiplier, Hardware Architecture, Shifted polynomial basis(SPB), Space Complexity, Time Complexity, XOR gate